The invention pertains to semiconductor constructions comprising damage (or gettering) regions; and also pertains to methods of forming semiconductor constructions comprising damage (or gettering) regions.
Impurity contamination of active area semiconductive materials is a problem within the semiconductor industry. Of particular concern are metallic contaminants, such iron, nickel and copper. When such impurities are present in semiconductive material of a device, the impurities can degrade the characteristics and reliability of the device. As integration in semiconductor devices becomes increasingly dense, the tolerance for metallic contaminants becomes increasingly stringent.
Among the methods for decreasing metallic contamination in semiconductor wafers are methods for improving cleanliness in semiconductor device manufacturing plants. However, regardless of how many steps are taken to insure clean production of semiconductor devices, some degree of contamination by metals seems inevitable. Accordingly, it is desirable to develop methods and structures for isolating metallic contaminants present in semiconductor wafers from devices which are ultimately formed within and upon such wafers. The act of isolating these contaminants is generally referred to as gettering, as the contaminants are gathered (typically physically and/or chemically), or gettered, to specific areas (referred to as xe2x80x9cproximity gettering regionsxe2x80x9d) within a semiconductor wafer.
Conventional processes for gettering metallic contaminants often focus on creating defects or damage within a semiconductor wafer in a region where gettering is sought to occur. Example embodiments of prior art methods for forming gettering regions are shown and described in U.S. Pat. Nos. 6,339,011 and 5,773,356, both of which are hereby incorporated by reference.
The methods described in U.S. Pat. Nos. 5,773,356 and 6,339,011 form damage regions within bulk semiconductive materials, with an exemplary bulk material being a bulk monocrystalline silicon wafer. The monocrystalline silicon wafer can be lightly background doped with p-type and/or n-type material. The wafer can be referred to as a semiconductor substrate. To aid in interpretation of the claims that follow, the terms xe2x80x9csemiconductive substratexe2x80x9d and xe2x80x9csemiconductor substratexe2x80x9d are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
A damage region can be formed within a semiconductive material substrate by implanting a neutral conductivity type dopant into the semiconductive material of the substrate. Exemplary neutral conductivity type dopants are H2, He, Ge, Ar, Si, O, C and N. The implanting of the dopants can be conducted at an energy of less than 1.0 MeV and at a current density of from 0.5 A/cm2 to 3.5 A/cm2. The damage formed within the One or more conductivity-enhancing dopants can be implanted around the damage region during incorporation of the damage region into a proximity gettering region. For instance, one or both of phosphorous and boron can be implanted into an area surrounding the damage region.
FIGS. 1 and 2 illustrate a cross-sectional view and top view, respectively, of a prior art proximity gettering region formed within a semiconductive material wafer. More specifically, FIGS. 1 and 2 illustrate a construction 10 comprising a semiconductive material substrate 12. The semiconductive material substrate 12 can be, for example, monocrystalline silicon lightly-doped with a background p-type dopant.
A proximity gettering region 14 is formed within substrate 12. Gettering region 14 comprises a damage region 16 and a conductively-doped region 18 surrounding region 16. Damage region 16 can be formed by, for example, implanting a neutral-type dopant into substrate 12. The implant disrupts a lattice of the semiconductive material to form extended crystal lattice defects within the semiconductive material. The defects can comprise, consist essentially of, or consist of vacancies in the crystalline lattice, and the term xe2x80x9cextendedxe2x80x9d indicates that the defects are larger than point defects. It is desirable that the implant utilized to form the damage region is at a low enough dose and duration that the crystalline semiconductive material is not appreciably converted to an amorphous form by the implant, and yet is at a high enough dose and duration to form the desired extended lattice defects. It is also desired that the defects be stable to a thermal budget less than or equal to that utilized in convention CMOS processing.
Doped region 18 can be formed by implanting a conductivity enhancing dopant into material 12 at a suitable depth to surround the damage region. The conductivity enhancing dopant of region 18 can be an opposite-type to that utilized in the background doping of material 12. Accordingly, if material 12 is background-doped with a p-type dopant, region 18 can be doped with an n-type dopant (such as, for example, phosphorous). Alternatively, if substrate 12 is background-doped with an n-type dopant, region 18 can be doped with a p-type dopant (such as, for example, boron).
Substrate 12 comprises an upper surface 15, and gettering region 14 is typically formed at a depth xe2x80x9cDxe2x80x9d of greater than 4 microns beneath upper surface 15. Gettering region 14 can be formed at such depth by implanting dopants through upper surface 15 and into the material 12 to a desired depth. Alternatively, a substrate can initially be provided to have an upper surface approximately coextensive with the location where gettering region 14 is ultimately to be formed. Gettering region 14 can then be formed by a shallow implant into the substrate to form the gettering region along the upper surface of the substrate. Subsequently, additional monocrystalline material can be epitaxially formed over the gettering region 14 to provide the material between gettering region 14 and upper surface 15.
Ultimately, various devices are formed to be supported by substrate 12. The devices can be formed over the substrate, and further can comprise portions within the substrate. For instance, the devices can include transistor devices having gates formed over the substrate and source/drain regions formed within the substrate. Various devices are illustrated diagrammatically in FIGS. 1 and 2 by blocks 20 and 22. Block 20 can correspond to a plurality of devices which are to be protected from metallic contaminants by gettering region 14. Such devices can include, for example, memory devices, and such would typically be arranged in an array. Exemplary memory devices are dynamic random access memory (DRAM) devices. As another example, the devices 20 can correspond to FLASH devices, such as, for example, erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM) devices.
As block 20 is a simplified schematic representation of devices, it can accordingly be referred to herein as devices 20. Further, in various applications block 20 can be considered a simplified schematic of an array of devices (such as memory devices), and in such applications block 20 can be considered an array 20.
Block 22 can be, in particular aspects, considered a simplified schematic representation of devices associated with a charge pump, and accordingly block 22 can be referred to herein as a charge pump 22. The charge pump generates electrons which are directed into substrate 12 to maintain a desired potential within the substrate. The electrons are illustrated diagrammatically by wavy lines 24 and 26 within FIG. 1.
A problem which can occur in utilizing gettering region 14 in combination with a charge pump is that some of the electrons generated by charge pump 22 can be deflected by either doped region 18 or damage region 16, and directed toward devices 20 (as illustrated by the path of electron 26). It is desired that the electrons instead follow the path of electron 24, whereby the electrons penetrate into material 12, and do not interfere with the operation of devices 20.
A method for avoiding the deflection of an electron 26 toward devices 20 is to separate the charge pump 22 from the devices by a large enough gap so that electrons from pump 22 don""t reach devices 20. Typically, the diffusion length of an electron in monocrystalline silicon (i.e., the distance that an electron can travel through monocrystalline silicon before it recombines with other materials and is effectively neutralized) is about 500 microns, on average. The average diffusion length for electrons can vary depending on the material that the electrons are diffusing through.
If material 12 is a substance in which an average diffusion length of an electron is 500 microns or less, then spacing of pump 22 from devices 20 by at least about 500 microns can alleviate, and possibly even prevent, problems associated with deflected electrons. However, such large separation between a charge pump and the devices consumes a substantial amount of semiconductor substrate real estate in the gap between the charge pump and the semiconductor devices. Semiconductor real estate becomes increasingly valuable as efforts are made to increase the density of devices across a semiconductor substrate. Accordingly, it would be desirable to develop alternative methods for removing the problem associated with deflected electrons 26.
Another method which has been utilized to avoid the problem with deflected electrons 26 is to bury gettering region 14 relatively deep beneath surface 15 of material 12. If gettering region 14 is at least 7 microns beneath surface 15, such increases a distance that deflected electrons need to travel to device 20 relative to shallower gettering regions, and such can alleviate, and even prevent, problems associated with deflected electrons 26. However, if the gettering region is too deep beneath devices 20, the gettering region does not function as well to protect the devices from metallic contaminants as would a shallower gettering region. Accordingly, it is desirable to develop alternative methods for avoiding the problems associated with deflected electrons 26 than simply increasing a depth of gettering region 14.
In one aspect, the invention encompasses a construction comprising an array of devices supported by a substrate comprising a semiconductive material. The array is bounded by an outer periphery. A damage region is within the semiconductive material of the substrate and under the array of devices. The damage region extends beyond the outer periphery of the array of devices by less than or equal to about one-half of an average electron diffusion length within the semiconductive material.
In one aspect, the invention encompasses a semiconductor construction comprising an array of devices and a charge pump supported by a semiconductive material substrate. A damage region is within the semiconductive material of the substrate and under the array of memory devices. The charge pump is separated from the array of memory devices by a distance, and the damage region extends less than or equal to 50% of the distance between the memory devices and the charge pump.
In one aspect, the invention encompasses a method of forming a semiconductor construction. A monocrystalline silicon substrate is provided, and a patterned masking layer is formed over the substrate. The patterned masking layer has first openings extending therethrough to expose regions of the substrate where alignment markings are to be formed. The first openings are extended into the exposed regions of the substrate to form the alignment markings. A second opening is formed into the masking layer over a section of the substrate which will ultimately be beneath an array of memory devices. A neutral-conductivity-type dopant is implanted through the second opening and into the section of the substrate to produce a damage region within the section. A first boundary extends laterally around the damage region. The masking layer is removed, and subsequently a layer of epitaxial silicon is formed over the monocrystalline silicon substrate. An array of memory devices is formed to be supported by the layer of epitaxial silicon. The array is bounded by a second boundary extending laterally around the array. The first boundary extends less than or equal to 100 microns beyond the second boundary.